ASML's High-NA EUV: How the $400M EXE:5200B Reshapes Chipmaking

Most coverage frames ASML High-NA EUV as the obvious next step every leading-edge fab will take. It isn't. TSMC, the company that builds chips for Nvidia, Apple, and AMD, has publicly said it will skip the technology for its 1.4nm A14 node and stick with older 0.33 NA EUV tools through the rest of the decade. That single decision tells you more about how the next five years of chip manufacturing will play out than any spec sheet.

The machines themselves are real, they work, and customers are running wafers through them. According to GuruFocus, ASML CEO Christophe Fouquet confirmed on May 19, 2026 that the first commercial chips made on High-NA EUV are expected to emerge "in the coming months." The disagreement is about whether they are worth it yet.

The number that explains everything: 0.55

Numerical aperture is the single spec that defines this generation of lithography. ASML's product page describes the EXE platform as moving from 0.33 NA on Low-NA EUV systems to 0.55 NA on High-NA, while still using the same 13.5nm extreme ultraviolet light source. The resolution improvement is concrete: features down to 8nm versus roughly 13nm on the older tools.

Think of it like the aperture on a camera lens. A wider aperture gathers more light at sharper angles, which lets the lens resolve finer detail at the focal plane. ASML widened the optical aperture of the scanner so it can resolve smaller circuit features in a single exposure, instead of requiring chipmakers to expose the same layer multiple times with offsets, a technique called multi-patterning.

That single-exposure capability is the entire commercial argument. ASML claims that by collapsing the number of process steps, fabs see reductions in defects, cost, and cycle time. Yahoo Finance reports that High-NA replaces the complex multi-patterning sequences previously needed with DUV, simplifying production and improving yield on the most advanced layers.

ASML EXE 5200B specs and what the $400 million buys

The TWINSCAN EXE:5200B is the first commercial High-NA system. ASML delivered the first unit in December 2023 and positions the platform for high-volume manufacturing in 2025 to 2026, aimed at 2nm logic nodes and advanced memory. The headline specs are 0.55 NA optics, an 8nm single-exposure resolution, and the same 13.5nm EUV plasma light source used on Low-NA systems.

The price is where the conversation gets uncomfortable. Per GuruFocus, citing Reuters, each High-NA machine carries a price tag of roughly $400 million, and customers are openly questioning the cost-benefit. Ad-hoc-news quoted TSMC deputy co-COO Kevin Zhang calling the machines "very, very expensive," with each unit north of €350 million.

For context on scale, Yahoo Finance reported that ASML shipped 48 EUV lithography systems and 131 immersion DUV tools across full-year 2025, generating €32.7 billion in total revenue against a €38.8 billion order backlog. High-NA is a small fraction of that fleet today, but a disproportionate share of the capital cost per fab.

How EUV lithography works, briefly, and why High-NA is harder

EUV produces 13.5nm light by firing a high-power CO2 laser at microscopic droplets of molten tin tens of thousands of times per second, creating a plasma that emits the right wavelength. Mirrors, not lenses, focus that light because no transparent material exists at 13.5nm. The light bounces through a stack of multilayer reflective optics, off a patterned reflective mask, and onto a silicon wafer coated with photoresist.

Widening the optical aperture from 0.33 to 0.55 forced ASML to redesign nearly the entire optical column. The reflective mirrors are larger and more precisely figured, the mask side uses an anamorphic optical design that demagnifies asymmetrically in the X and Y directions, and the wafer stage has to step through smaller exposure fields at higher speed. None of that is incremental engineering. It is a new scanner platform that happens to share a light source.

The consequence chipmakers care about: the rest of the supply chain has to catch up. TrendForce notes that Intel, Samsung, and others must simultaneously co-develop new masks, etching processes, resolution-enhancement techniques, and metrology tools before High-NA can be fully exploited. The scanner is the easy part.

ASML High-NA vs Low-NA: why TSMC is walking away from the obvious upgrade

The pitch for High-NA is straightforward. A single 0.55 NA exposure replaces two or three 0.33 NA exposures on critical layers, cutting steps, defects, and turnaround time. The pitch against it is equally straightforward: at roughly $400 million per scanner, you have to print a lot of wafers before that capital pays back compared to amortizing existing Low-NA tools through clever multi-patterning.

TSMC has done the math and chosen the second path. According to SmBom, citing Kevin Zhang, TSMC has no plans to use High-NA for its A14 process and believes its standard EUV systems are sufficient to support leading-edge production through 2026 and into the A16 node. Wccftech reports TSMC will refrain from using ASML's most advanced EUV machines through 2029, with A14 in 2028 and A13/A12 arriving in 2029 still on Low-NA tooling.

Intel made the opposite call. TrendForce reports Intel deployed the industry's first High-NA system, announced acceptance of the TWINSCAN EXE:5200B in December 2025, and is aiming the platform at its Intel 14A process node. Epium reports Intel has already processed more than 30,000 trial wafers at 14A on the new equipment. Samsung sits between them, with a first High-NA scanner installed in late 2025 and a second in the first half of 2026, per TrendForce.

This is the most important structural fact about the next five years of leading-edge logic: the three companies capable of building 1.4nm-class chips have picked three different lithography strategies. That divergence is unprecedented at the bleeding edge, and it changes who can supply whom. If you want to read more on how the foundry race is reshaping CPU roadmaps, our coverage of Intel Panther Lake and the 18A node lays out the other half of the picture.

High-NA EUV lithography explained through the one trade-off nobody markets

The specification that predicts real-world adoption better than NA or resolution is the exposure field size. Because of the anamorphic optics, a single High-NA exposure covers roughly half the wafer area of a Low-NA exposure. To pattern a full reticle-sized die, the scanner has to stitch two High-NA shots together with sub-nanometer alignment. For large dies, common in AI accelerators and server CPUs, that stitching introduces overlay risk that does not exist on Low-NA.

This is the buried spec. It is also why TSMC's gamble looks more defensible than the headline price tag suggests. Multi-patterning on Low-NA is well understood, and the company has a decade of yield data on it. High-NA stitching is new, and yield on the largest, most expensive dies is exactly where mistakes hurt most.

Cloudnews summarised ASML's SPIE 2026 roadmap directly: Low-NA EUV tools continue to evolve, High-NA is entering early production, and Hyper-NA at 0.75 NA is emerging as a concept for beyond 2030. DUV, Low-NA EUV, and High-NA EUV are expected to coexist for years, with adoption described as a "prolonged coexistence" rather than a clean generational swap.

Next-gen chip manufacturing 2026 is not waiting on a single tool

High-NA is shipping, working, and producing wafers. Yahoo Finance reports more than 300,000 wafers had already been processed at customer sites on High-NA equipment and ASML expects its EUV business to grow rapidly through 2026 on advanced DRAM and leading-edge logic demand, while DUV declines relative to 2025 levels. TrendForce cites Nikkei in noting the 0.55 NA machines are suited for mass production of 1.4nm logic and 10nm-class DRAM and below.

The market is still tilting toward ASML regardless of which customer adopts what. GuruFocus puts ASML's global share of semiconductor lithography at roughly 90 percent and its market capitalisation near $562.5 billion as of May 2026. Cloudnews reports ASML raised its full-year 2026 revenue forecast to €36 to €40 billion at a 51 to 53 percent gross margin, driven primarily by AI-related demand.

The key implication for anyone tracking the industry: do not read High-NA adoption as a proxy for who is winning the foundry race. Intel is betting High-NA gives it a process-leadership lever that pure capacity cannot. TSMC is betting that yield, capital efficiency, and customer cost matter more than being first on the newest scanner. Both bets can be correct simultaneously, for different customers. The chips landing in 2027 and 2028 from each fab will settle the argument, and until then, the cleanest signal to watch is not ASML's order book but the defect-density numbers that Intel and TSMC publish at their respective technology symposia. That is where High-NA either justifies $400 million or doesn't.

For related reading on the silicon stack underneath today's AI boom, see our explainer on how Cerebras' wafer-scale engine works and the broader AI Infrastructure coverage.